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1st Joint SpeAC/Fleur Workshop, January 24-25, 2002 in Grenoble


Programme and Presentations


Thursday, January 24, 2002
  12:00            Registration, welcome and lunch buffet

Session 1: System level specification and IP-based SoC design
13:00 - 13:25 Bridging the gap between concept engineering and development R. Kress, Infineon, Germany 13:25 - 13:50 Specification of multi-domain systems based on Matlab M. Stark, A. Reutter, Robert Bosch GmbH, Germany 13:50 - 14:15 Interfacing concept for different levels of abstraction in IP-based SoC designs S. Verdenhalven, H. Kuehl, sci-worx GmbH, Germany 14:15 - 14:40 Specification and validation methodologies for heterogeneous SoCs G. Nicolescu, L. Gauthier, D. Lyonnard, W. Cesário, TIMA, France 14:40 - 15:05 High Level energy modeling and exploration for ultra low-power VLIW embedded processors Roberto Zafalon, ST, Italy 15:05 - 15:35 Break
Session 2: System level evaluation and synthesis in platform-based design
15:35 - 16:00 VCC and its value for SpeAC G. Martin, F. Hussmann, Cadence, Germany 16:00 - 16:25 Communication analysis in multi-process synthesis O. Bringmann, FZI, Germany 16:25 - 16:50 Automatic OS and HW/SW interface generation for communication and macro architecture refinement of multiprocessor SoC architectures W. Cesário, L. Gauthier, D. Lyonnard, G. Nicolescu, TIMA, France 16:50 - 17:15 HW/SW interface generation for SoC IP integration using standard bus I. Moussa, T. Roudier, TNI-Valiosys, France 17:15 - Joint SpeAC/Fleur PMT meeting 20:00 Social Dinner
Friday, January 25, 2002
Session 3: Validation and emulation for different target architectures
9:00 - 9:25 Language integration for future SoC design R. Ernst, TU Braunschweig (Subcontractor of Astrium), Germany 9:25 - 9:50 Studies on instruction set emulation for rapid protoyping of SoCs J. Schnerr, University of Tuebingen (Subcontractor of Infineon), Germany 9:50 - 10:15 Instruction Set Simulation at System Level? Motivation and Status J. Sturm, Melexis, Germany 10:15 - 10:40 Co-validation of radio digital front end with ADS B. Candaele, D. Merel, M. Sarlotte, Thales, France 10:40 - 11:05 System prototyping and debug M. Pavesi, Italtel, Italy 11:05 - 13:00 German review meeting


Last modified: January 10, 2002 by Oliver Bringmann, FZI.