SpeAC - MEDEA+ Project A508

Publications


  • U. Badelt, M. Radetzki, H. Kühl: “sciPROVE: C++ Based Ve-rification Environment for IP and SoC Design”, Forum on specification & Design Languages 2003 (FDL’03), Frankfurt /M, 23.-26. September 2003.
  • U. Badelt, M. Radetzki: “sciPROVE - C++ based verification environment”, Präsentation auf der DAC 2002 (Cadence Stand), New Orleans (USA), June 2002.
  • N. Bannow, K. Haug: “Performance Analysis and Automated C++ Modularization with the Usage of Module-Adapters for SystemC”, Forum on Specification & Design Languages (FDL), Lille, France, 2004.
  • P. Birrer, W. Hartong, S. J. Chandrasekaran, ” Nutzung von SystemC-Modulen innerhalb eines Analog/Mixed-Signal Designablaufs”, Analog 2005, March 2005, Hannover.
  • O. Bopp: “Automatisierung der Schnittstellengenerierung zwischen dem VHDL-Simulator Modelsim und C-Modulen”, Master’s Thesis, 2002, Reutlingen, Germany
  • O. Bopp: “Beschreibung einer sicherheitskritischen Automobil-Applikation in SystemC”, Bosch Technical Report, 2001, Reutlingen, Germany
  • A. Braun: T. Schubert, M. Stark, K. Haug, J. Gerlach, W. Rosenstiel, “Case Study: SystemC-Based Design of an Industrial Exposure Control Unit”, Forum on Specification & Design Languages (FDL), September 23.-26., 2003, Frankfurt, Germany.
  • A. G. Braun, T. Schubert, M. Stark, K. Haug, J. Gerlach, W. Rosenstiel , ”A Case Study: SystemC-Based Design of an Industrial Exposure Control Unit”, in C. Grimm (ed.), “Languages for System Specification”, Chapter 8 (pp. 119-132), Kluwer Academic Publishers, 2004.
  • O. Bringmann: “Synchronisationsanalyse zur Multi-Prozeß-Synthese”, Logos-Verlag, 2003.
  • O. Bringmann: “SystemC vs. SystemVerilog – Anwendungsgebiete und Trends –”, Fach- und Kooperations-Workshop: "Modellierung und SystemC", October 7-8, 2003, Hanover, Germany.
  • O. Bringmann, A. Braun, W. Rosenstiel: “Specification and Design Data Exchange of Micro Electronic Hardware/Software Systems using SystemC”, 6th NASA-ESA Workshop on Product Data Exchange - Open Standards for Model-Based Development, 2004.
  • O. Bringmann, W. Rosenstiel: “Transaction Level Modelling in System Design”, MEDEA+ Design Automation Conference, Château des Mesnuls, France, May 24 – 26, 2005.
  • O. Bringmann: “Research Challenges Towards a Coherent TLM Methodology”, Workshop on Efficient Transaction Level Modelling, June 30, 2005, Paris, France.
  • O. Bringmann,, A. Siebenborn, W. Rosenstiel: “Conflict Analysis in Multiprocess Synthesis for Optimized System Integration”, International Conference on Hardware - Software Codesign and System Synthesis New York, USA, Sept. 19-21, 2005.
  • K. Buchenrieder (Hrsg): “Hardware/Software Codesign”, 2. erweiterte Auflage, IT-Press, 2001, ISBN: 3-929814-26-9.
  • K. Buchenrieder, A. Pyttel, and A. Sedlmeier: “A powerful System Design Methodology combining OCAPI and Handel-C for Concept Engineering”, In: Proceedings of Design Automation and Test in Europe, DATE, Paris, 2002.
  • S. Bulach: “Design of Automotive Electronic Systems using SystemC and Matlab/Simulink”, Kooperations-Workshop: Modellierung und SystemC, October, 07-08, 2003, Hannover, Germany
  • B. Candaele: “Frontiers between System and SoC”, French SOC Day, Grenoble, May 29th 2002.
  • B. Candaele: “SoC integration and validation in Telecom applications”, 7th IEEE Conference HLDVT’02, Invited paper, Cannes, October 28-29th 2002.
  • W. Cesário: “Abstract Architecture Model for SoC Made of Heterogeneous Components”, MEDEA+ Design Automation Conference, Stuttgart, Germany, 2003.
  • W. Cesário, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu,  Y. Paviot,  S. Yoo, A. A. Jerraya, M. Diaz-Nava: “Component-Based Design Approach for Multicore SoCs”, DAC 2002, June 10-14 2002, New Orleans, USA.
  • W. Cesário, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, L. Gauthier, M. Diaz-Nava, A. A. Jerraya: “Multiprocessor SoC Platforms: A Component-Based Design Approach”, IEEE Design & Test of Computers,Vol. 19 Nr. 6,  Nov-Dec, 2002.
  • W. Cesário:    “Hardware Software communication interfaces abstraction for SoC”, MEDEA+ Design Automation Conference, Stresa, Italy, 2002.
  • W. Cesário, Y. Paviot, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, S. Yoo, A. A. Jerraya, M. Diaz-Nava: “HW/SW Interfaces Design of a VDSL Modem using Automatic Refinement of a Virtual Architecture Specification into a Multiprocessor SoC: a Case Study”, DATE 2002, Paris, France, March 2002.
  • W. Cesário, F. R. Wagner, A. A. Jerraya, “Hardware/Software Interfaces Design for SoC”, chapter 13 section VI in “The Industrial Information Technology Handbook”, CRC Press, 2004.
  • W. Cesário, Y. Paviot, L. Gauthier, D. Lyonnard, G. Nicolescu, S. Yoo, A.A. Jerraya, "Object-based Hardware/Software Component Interconnection Model for Interface Design in System-on-a-chip Circuits", The Journal of Systems and Software, SI: Rapid System Prototyping, Ed. by L.M. Wills, F. Kordon and Luqi, Vol. 70/3 pp. 229-244, Elsevier Science, 2004.
  • S. Chakraborty, L. Thiele: “A New Task Model for Streaming Applications and its Schedulability Analysis”. Design Automation and Test in Europe (DATE), Munich, Germany, March, 2005.
  • S. Chakraborty, S. Künzli, L. Thiele: “A General Framework for Analysing System Properties in Platform-Based Embedded System Designs”. Design Automation and Test in Europe (DATE), Munich, Germany, March, 2003.
  • S. Chakraborty, S. Künzli, L. Thiele, A. Herkersdorf, P. Sagmeister: “Fast and Accurate Performance Evaluation of Network Processor Architectures: Combining Simulation with Analytical Estimation”. Computer Networks, 2003.
  • S. Chakraborty, M. Gries, L. Thiele: “Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic”. 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), IEEE Press, San Jose, California, September, 2002.
  • S. Chakraborty, S. Künzli, L. Thiele, A. Herkersdorf, P. Sagmeister: “Fast and Accurate Performance Evaluation of Network Processor Architectures: Combining Simulation with Analytical Estimation”. Computer Networks and ISDN Systems, 2002.
  • S. Chakraborty, S. Künzli, L. Thiele: “Approximate Schedulability Analysis”, 23rd Real Time System Symposium (RTSS), Austin, TX, 2002
  • S. Chakraborty, T. Erlebach, S. Künzli, L. Thiele: “Schedulability of Event-Driven Code Blocks in Real-Time Embedded Systems”. 39th Design Automation Conference (DAC 2002), New Orleans LA, USA, June, 2002.
  • M. A. Dziri, F. R. Wagner, W. Cesário and A. A. Jerraya, “Unified Component Integration Flow for MPSoC Design And Validation Proceedings of DATE, Paris, 2004.
  • M. A. Dziri, F. Samet, F. R. Wagner, W. O. Cesário, A. A. Jerraya, “Combining Architecture Exploration and a Path to Implementation to Build a Complete SoC Design Flow from System Specification to RTL”, ASP-DAC 2003, Kitakyushu, Japan, January 2003.
  • R. Ernst: “Putting it all together” (invited paper). ACM Queue, pp. 50 – 55, April 2003.
  • J. Gerlach and W. Rosenstiel: “System Level Design. Using the SystemC Modeling Platform”; In: Merker, Schwarz (Eds.): System Design Automation, pp. 27-34, Kluwer Academic Publisher 2001, ISBN 0-7923-7313-8.
  • J. Gerlach: “Co-Simulation zur Validierung heterogener Systeme des Automobilbereichs”, Bosch Kommunikationsforum Gesamtsimulation, December 2, 2002, Reutlingen, Germany.
  • J. Gerlach: “Design of Automotive Electronic Systems using SystemC and Matlab/Simulink” (Poster), MEDEA+ Design Automation Conference, November 04-06, 2003, Stuttgart, Germany
  • J. Gerlach: “Design of Automotive Electronic Systems using SystemC and Matlab/Simulink” (Poster), MEDEA+ Forum 2003, Berlin, November 25-26, 2003.
  • J. Gerlach, „Simulink-basierte Modellierung und Synthese von digitalen Systemen der Automobilelektronik“, 3. EkompaSS Workshop „Entwurfsplattformen komplexer angewandter Systeme und Schaltungen“, May 18-19, 2004, Hannover, Germany.
  • J. Gerlach: “Specification Methods and Languages for Automotive Applications”, MEDEA+ Design Automation Conference, October 23-25, 2002, Stresa, Italy.
  • J. Gerlach: “Spezifikationsbasierter Entwurf von Automotive-Systemen”, 2. EkompaSS Workshop Entwurfsplattformen komplexer angewandter Systeme und Schaltungen, April 29-30, Hannover, Germany, 2003.
  • J. Gerlach, “Methodik und Werkzeugumgebung zum Simulink-basierten Entwurf von automobilelektronischen Systemen”, Fach- und Kooperationsworkshop „Matlab-Integration und Performanzanalyse“, December 8, 2004, Dresden, Germany.
  • J. Gerlach, “Simulink-basierte Modellierung und Synthese von digitalen Systemen der Automobilelektronik”, 3. EkompaSS Workshop “Entwurfsplattformen komplexer angewandter Systeme und Schaltungen”, Mai 18-19, 2004, Hannover, Germany
  • J. Gerlach, “Einbettung des digitalen Designflows in eine Simulink-basierte Entwurfsmethodik”, 4. EkompaSS Workshop “Entwurfsplattformen komplexer angewandter Systeme und Schaltungen”, April 26-27, 2005, Hannover, Germany.
  • J. Gerlach, „Embedding the Digital Hardware Implementation Flow into a Simulink Based System Design Methodology“, 3nd Open SpeAC Workshop, June 22, 2005, Friedrichshafen, Germany.
  • P. Ganal: “Complex SOC Designs: Change or Challenge for SME Service Providers?”, 2nd Open SpeAC Workshop, DATE 2004, Paris, 2004.
  • P. Ganal: “System House / SME Supply Chain in Distributed SoC Design”, 3nd Open SpeAC Workshop, Friedrichshafen, 2005.
  • J. Greutert: “Modeling and implementation of software for SoC, Modelling, Verification, and Synthesis with SystemC - Principles and Examples”, MEDEA+ Design Automation Conference, Stuttgart, Germany, 2003.
  • J. Greutert, L. Thiele: “RNOS – A Middleware Platform for Low Cost Packet Processing Devices”. 3rd Workshop on Network Processors (NP3), held in conjunction with HPCA10, Madrid Spain, February, 2004.
  • J. Greutert, L. Thiele: “RNOS – A Middleware Platform for Low Cost Packet Processing Devices”, Bookchapter in: “Network Processor Design, Issues and Practices Vol. 3, Morgan Kaufmann Publishers, 2005.
  • M. Hahn: “Modellierung von Mikroprozessorsystemen mit Matlab/Simulink”, Workshop Multi-Nature Systems, Ilmenau, Germany, 2003.
  • M. Hahn, J. Sturm: “Modellierung von Mikroprozessorsystemen in Matlab/Simulink”, Workshop Embedded Mixed Signal Systems, IMMS, Erfurt, 06. Nov. 2002.
  • M. Hahn: “Modeling Microprozessor Systems”, IMMS Annual Report, 2002.
  • C. Hansen, O. Bringmann, W. Rosenstiel: “A VHDL Reuse Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis”. In “Virtual Components Design and Reuse” edited by R. Seepold and N. Martinez, Kluwer Acad. Publ., 2001.
  • W. Hartong: "Bridging the Gap from System Design to Mixed-Signal IC Implementation with SystemC", DATE, Paris, Feb. 2004.
  • W. Hartong, “From System to Analog – Narrow the Gap!“, 3nd Open SpeAC Workshop, June 22, 2005, Friedrichshafen, Germany.
  • G. Haug and W. Rosenstiel: “VLIW-Prozessorbasierte Emulation und Prototyping digitaler Schaltungen”, In: Entwurf Integrierter Schaltungen, 10. E.I.S.-Workshop, 3.-5. April 2001, Dresden, pp. 111-116, ISBN 3-8007-26084.
  • R. Hoffer, A. Brüning: “A Module Interface Layer Based IP Core Verification and Validation Scheme”. Forum on Specification & Design Languages (FDL), Lille, 2004.
  • R. Hoffer: “sciPROVE: sci-worx' C++ Based Verification Environment for IP and SoC Design”, SpeAC Workshop, Paris, Feb. 2004.
  • R. Hoffer, F. Baszynski: "Implementation of a SystemC based Environment for SoC Verification and Validation", accepted for FDL Workshop, Lausanne, Sep. 2005.
  • R. Hoffer: "sciPROVE 2.0: SystemC based Environment for SoC Verification and Validation", SpeAC Workshop, June 2005.
  • Jenck: “Evaluation of a New Tool for C Based Architectural Synthesis”, Master Thesis, Ecole Supérieure de Chimie Physique Electronique de Lyon, 2001, Lyon, France
  • R. Kress: “SoC Development Challenges”. Keynote at the Int. Conference on Rapid Systems Prototyping, Darmstadt, July, 2002.
  • J. Kruse, C. Thomsen, R. Ernst: "The Role of Estimations in Inter-Company Refinement Cycles" 2nd Open SpeAC Workshop, DATE 2004, 20. February 2004, Paris
  • J. Kruse, T. Volling, C. Thomsen, R. Ernst, T. Spengler: “Towards Flexible Systems Engineering by Using Flexible Quantity Contracts”. Proceedings of AAET, Braunschweig, 2005
  • J. Kruse, T. Volling, C. Thomsen, R. Ernst, T. Spengler: “Introducing Flexible Quantity Contracts into Distributed SoC and Embedded System Design Processes”. Proceedings of DATE, Munich, 2005
  • J. Kruse, T. Volling, C. Thomsen, R. Ernst, T. Spengler: “Flexible SoC Engineering via Flexible Quantity Contracts”. 3rd Open SpeAC Workshop, Friedrichshafen, 2005
  • S. Künzli: Design Space Exploration for Network Processor Architectures, 2nd Open SpeAC Workshop, Paris, France, February 2004.
  • S. Künzli, S. Bleuler, L. Thiele and E. Zitzler: A Computer Engineering Benchmark Application for Multiobjective Optimizers,  Bookchapter in "Applications of Multi-  Objective Evolutionary Algorithms", Editors: Carlos A. Coello Coello and Gary B. Lamont, World Scientific Publishing, December 2004.
  • S. Künzli, L. Thiele, E. Zitzler: Modular Design Space Exploration Framework for Embedded Systems. IEE Proceedings Computers & Digital Techniques, Vol. 152, No. 2, pages 183-192, March, 2005.
  • S. Künzli: Performance evaluation of networking systems: Combination of formal analysis with measurement system, 3rd Open SpeAC Workshop, Friedrichshafen, Germany, June 2005.
  • S. Künzli, L. Thiele, E. Zitzler: Multi-criteria Decision Making in Embedded System Design. Book Chapter in: “SoC: Next Generation Electronics”, 2005.
  • T. Kuhn, T. Oppold, M. Winterholer, W.  Rosenstiel, M.  Edwards, Y. Kashai: “A Framework for Object Oriented Hardware, Specification, Verification, and Synthesis”. Proceedings of Design Automation Conference (DAC), 2001.
  • T. Kuhn, T. Oppold, M. Winterholer, W.  Rosenstiel, M.  Edwards, Y. Kashai: “Object Oriented Hardware Synthesis and Verification”. 14th International Symposium on System Synthesis (ISSS’01), Montréal, Québec, Canada, 2001.
  • D. Lettnin, A. Braun, M. Bogdan, J. Gerlach, W. Rosenstiel: “Synthesis of Embedded SystemC Design: A Case Study of Digital Neuronal Networks”, Proceedings of DATE, Paris, 2004.
  • G. Lutz, M. Delic, P. Boysen: "Concept of an Integration Platform for the Support of Distributed Engineering Processes" 2nd Open SpeAC Workshop, DATE 2004, 20. February 2004, Paris.
  • G. Lutz:  "XML based integration platform ", 3rd Open SpeAC workshop, June 2005, Friedrichshafen
  • D. Lyonnard, S. Yoo, A. Baghdadi, A. A. Jerraya: “Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip”; Design Automation Conference, Las Vegas, 2001.
  • D. Matolin: “Co-Simulation Simulink/Modelsim”, Bosch Technical Report, 2002, Reutlingen, Germany
  • D. Maufroid, P. Kajfasz, B. Candaele: “mAgic-FPU and MADE : a customisable VLIW core and the modular VLIW processor architecture description environment”, Computer Physics Communications, 13/2001.
  • A. Maxiaguine, S. Künzli, L. Thiele: “Workload Characterization Model for Tasks with Variable Execution Demand”. DATE 2004, February, 2004.
  • A. Maxiaguine, S. Künzli, S. Chakraborty, L. Thiele: “Rate Analysis for Streaming Applications with On-Chip Buffer Constraints”. ASP-DAC 2004, Yokohama, Japan, January, 2004.
  • A. Maxiaguine, S. Chakraborty, S. Künzli and L. Thiele: Evaluating Schedulers for Multimedia Processing on Buffer-Constrained SoC Platforms,  IEEE Design & Test,  Vol. 21, No. 5, pages 368-377, Sep./Oct. 2004
  • Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakraborty, Weng-Fai Wong: Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs. CODES+ISSS 2004: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, ACM Press, Stockholm, Sweden, pages 128-133, 2004
  • C. Menn, O. Bringmann, W. Rosenstiel: “Controller Estimation for FPGA Target Architectures During High-Level Synthesis”. Proceedings of International Symposium on System Synthesis, Kyoto, Japan, 2002.
  • C. Menn: “Hardware-Abschätzung für High-Level Spezifikationen digitaler Schaltungen”, Logos-Verlag, Berlin, 2005.
  • W. Müller, W. Rosenstiel, J. Ruf (Eds.), “SystemC-Methodologies and Applications”, Kluwer Academic Publisher, 2003.
  • D. Müller, J. Ruf, D. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiel: “The Simulation Semantics of SystemC”, In: Proceedings Design Automation and Test in Europe, DATE 2001, pp. 64-70, ISBN 0-7695-0993-2.
  • R. Müller: “Systems Engineering and Distributed Design for Space Applications”, 2nd Open SpeAC Workshop, DATE 2004, 20. February 2004, Paris.
  • R. Müller, H. Eisenmann: “Distributed Design Methods for Space Applications”,  6th NASA-ESA Workshop on Product Data Exchange - Open Standards for Model-Based Development, 22. April 2004, Friedrichshafen.
  • R. Müller, H. Eisenmann, O. Ried: "Systems Engineering Methodology Applied On A Distributed System-On-Chip Development”, MEDEA+ Design and Automation Conference, May 2005, Chateau des Mesnuls, France.
  • R. Müller, H. Eisenmann, O. Ried: "Systems Engineering Methodology Applied On A Distributed System-On-Chip Development”,  ProData Systems in Aerospace DASIA Conference, June 2005, Edinburgh, Scotland.
  • R. Münzenberg, F. Slomka, M. Dörfel, O. Bringmann: “Method for Producing Computer-Assisted Real-Time Systems”, International patent WO0221261 A3, 18.07.2002, German Patent DE 10057651 C2, 22.05.2003, EU patent EP1325410 A2, 09.07.2003, and US Patent US2004027924, 12.02.2004.
  • U. Nageldinger, Th. Wilde, R. Schwencker, J. Eckmüller: "A SystemC-based Modeling Methodology for complex ICs"; MEDEA+ DAC 2005, Chateau des Mesnuls, France, May 2005.
  • U. Nageldinger, A. Pyttel, H. Kleve: "System Simulation Speedup Combining SystemC Models and Reconfigurable Hardware", SpeAC Workshop, Paris, Feb. 2004.
  • H.-N. Nguyen, M. Sarlotte, C. Antoine, S. Emeriau:  “Verification of DSP IP Cores by Model Checking”, 7th IEEE Conference HLDVT’02, Cannes, October 27-29th 2002.
  • H.-N. Nguyen: “A Meet-in-the-Middle Verification Strategy”, Proceedings of the IP-Based SoC Design Workshop, December 6-7, 2001, Grenoble, 2001.
  • J.-H. Oetjens, A. Reutter: “Entwickler-Leitfaden: Einsatz von Bestbench im Automotive-Designflow”, Bosch Technical Report, 2001, Reutlingen, Germany
  • J.-H. Oetjens: “Konzeption und Implementierung eines Systems zur automatisierten Generierung von VHDL aus Simulink-Modellen”, Master’s Thesis, 2002, Reutlingen, Germany
  • J.-H. Oetjens, J. Gerlach, W. Rosenstiel: „Ein XML-basierter Ansatz zur flexiblen Darstellung und Transformation von Schaltungsbeschreibungen”, GI/ITG/GMM Workshop „Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, February 24-25, 2004, Kaiserslautern, Germany.
  • J.-H. Oetjens, J. Gerlach, W. Rosenstiel: “An XML Based Approach for Flexible Representation and Transformation of System Descriptions”. Forum on Specification & Design Languages (FDL), Lille, France, 2004.
  • T. Pflug: “Hardware Description and Synthesis with SystemC”, Master Thesis, University of Applied Sciences Mittweida (FH), 2002, Leonberg, Germany.
  • M. Pavesi: “Rapid Prototyping: players, issues and trends”, MEDEA+ Design Automation Conference, Stresa, Italy, 2002.
  • J.Quevremont, M.Sarlotte, B.Candaele, “Specification and architecture exploration for DSP system platforms” February 10, 2004, Paris, France.
  • T. Rentschler: “FPGA-basierte Belichtungsregelung von CMOS-Kameras für Automobilanwendungen”, Master Thesis, Pforzheim University of Applied Sciences, 2001, Pforzheim, Germany
  • A. Reutter: “Specification methods and languages for automotive applications”, MEDEA+ Design Automation Conference, Stresa, Italy, 2002.
  • A. Reutter: “Systemspezifikation und -entwurf im Automotive-Designflow”, Bosch DIC (Design of Integrated Circuits) Workshop, June 28, 2002, Reutlingen, Germany.
  • K. Richter, M. Jersak, R. Ernst: “A Formal Approach to MpSoC Performance Verification”. IEEE Computer, pp. 60 – 67, April 2003.
  • O. Ried:  "IP Integration with standardized XML", 3rd Open SpeAC workshop, June 2005, Friedrichshafen.
  • W. Rosenstiel: “Modelling, Verification, and Synthesis with SystemC - Principles and Examples”, MEDEA+ Design Automation Conference, Stuttgart, Germany, 2003.
  • W. Rosenstiel: “Platform Based Design of Embedded Systems in SystemC”, MEDEA+ Design Automation Conference, Stresa, Italy, 2002.
  • S. Schmitt, W. Rosenstiel: “Verification of a Microcontroller IP Core for SoC Designs Using Low-Cost Prototyping Environments”, Designers Forum, DATE, 2004.
  • J. Schnerr, G. Haug, W. Rosenstiel: “Instruction set emulation for rapid prototyping of SoCs”, Proceedings of DATE, Munich, 2003.
  • J. Schnerr, O. Bringmann, W. Rosenstiel: “Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs”, Proceedings of DATE, Munich, 2005.
  • C. Schulz-Key, M. Winterholer, T. Schweizer, T. Kuhn, W. Rosenstiel: “Object-Oriented Hardware Design and Synthesis with SystemC”. Forum on Specification & Design Languages (FDL), Lille, France, 2004.
  • C. Schulz-Key, M. Winterholer, T. Schweizer, T. Kuhn, and W. Rosenstiel: “Object-Oriented Modeling and Synthesis of SystemC Specifications”. Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC’04), Yokohama, Japan, 2004.
  • C. Schulz-Key C., T. Kuhn., and W. Rosenstiel: “A Framework for System-Level Partitioning of Object-Oriented Specifications”. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI’2001), Nara, Japan, 2001.
  • T. Schubert, J. Hanisch, J. Gerlach, J.-E. Appell, W. Nebel: “Evaluation of a Refinement-Driven SystemC-Based Design Flow”, Design Automation and Test in Europe (DATE) 2004, Designer’s Forum, February 17-19, 2004.
  • T. Schubert, J. Hanisch, J. Gerlach, J.-E. Appell, W. Nebel, “Evaluation of a Refinement-Driven SystemC-Based Design Flow”, in ”Selected Readings on Embedded HW/SW-Systems”, J. Appell, W. Nebel, F. Slomka (Eds.), bis (Bibliotheks- und Informationssystem der Universität Oldenburg), Vol. 1-2004-04-21, 2004.
  • A. Siebenborn, O. Bringmann, W. Rosenstiel:  “Worst-Case Performance Analysis of Parallel, Communicating Software Processes”. Proceedings of International Symposium on Hardware/Software Co-Design, Estes Park, Colorado, USA, 2002.
  • A. Siebenborn, O. Bringmann, W. Rosenstiel:  “Communication Analysis for System-on-Chip Design”. Proceedings of DATE, Paris, 2004.
  • A. Siebenborn, O. Bringmann, W. Rosenstiel: “Communication Analysis for Network-on-Chip”. Proceedings of PARELEC, 2004.
  • A. Siebenborn, O. Bringmann: “Performanz- und Konfliktanalyse zur optimierten Busallokierung”, Fach- und Kooperationsworkshop Matlab-Integration und Performanzanalyse, edacentrum, Dresden, Germany, 2004.
  • M. Stark, A. Braun, W. Rosenstiel: “A Flexible Methodology for the XML-based Automated Interface Generation in Co-Simulation”, DASS/SDA-Workshop, May, 2003.
  • M. Stark, A. Reutter: “Specification of Multi-Domain Systems Based on Matlab”, 1st Joint Workshop SpeAC/Fleur, January 24-25, 2002, Grenoble, France
  • M. Stark, J. Gerlach: “Specification-Based Design of Multi-Domain Systems based on Matlab/Simulink”, MEDEA+ Design Automation Conference, October 23-25, 2002.
  • M. Stark, J. Oetjens, W. Rosenstiel: “A Seamless Simulink based System Design Flow for Automotive Applications”, Forum on Specification & Design Languages (FDL), September 23-26, 2003, Frankfurt a.M., Germany, 2003.
  • M. Stark: “HDL-Codegenerierung aus Simulink”, 2. EkompaSS Workshop, Hannover, Germany, April 29-30,
  • M. Stark: “Specification and Algorithm/Architecture-Co-Design for Highly Complex Applications in Automotive”, Bosch Ph.D. Forum, Reutlingen, December 9, 2002.
  • M. Stark: “Spezifikationsbasierter Systementwurf mit Matlab/Simulink”, Bosch DIC (Design of Integrated Circuits) Workshop, Reutlingen, May 28, 2002.
  • M. Stark: “Systementwurfsmethoden im Automobilbereich”, Bosch internal presentation, April 3,2003, Reutlingen, Germany
  • J. Sturm: “Instruction Set Simulation at System Level? Motivation and Status”, SpeAC/Fleur Workshop, TIMA, Grenoble, 24./25. Jan. 2002
  • L. Thiele, S. Chakraborty, M. Gries, S. Künzli: “A Framework for Evaluating Design Tradeoffs in Packet Processing Architectures”. 39th Design Automation Conference (DAC 2002), New Orleans LA, USA, June, 2002.
  • L. Thiele, S. Chakraborty, M. Gries, S. Künzli: “Design Space Exploration of Network Processor Architectures”. First Workshop on Network Processors at the 8th International Symposium on High-Performance Computer Architecture (HPCA8), Cambridge MA, USA, February, 2002.
  • L. Thiele, S. Chakraborty, M. Gries, S. Künzli: “Design Space Exploration of Network Processor Architectures”. Bookchapter in: “Network Processor Design Issues and Practices Vol. 1”, Morgan Kaufmann Publishers, 2002.
  • E. Ulicna: “Heterogeneous multi-abstraction level simulation and co-simulation”, MEDEA+ A508 SpeAC Workshop at DATE, Paris, Nov. 2004.
  • E. Ulicna: “Heterogeneous Multi-Abstraction Level Simulation and Co-Simulation of Electronic Control Units for Automotive Applications”, 3rd open SpeAC workshop, Friedrichshafen, June 29, 2005.
  • A. Viehl, O. Bringmann,  W. Rosenstiel: “Performance Analysis of Sequence Diagrams for SoC Design”, Proceedings of 2nd UML for SoC Design Workshop at 42nd Design Automation Conference (DAC), Anaheim, USA, 2005.
  • A. Viehl, O. Bringmann,  W. Rosenstiel: “Control-Flow Aware Communication and Conflict Analysis”, 3rd open SpeAC workshop, Friedrichshafen, June 29, 2005.
  • S. Verdenhalven, H. Kühl: “Interfacing Concept for Different Levels of Abstraction in IP-based SoC Design”, 1st open SpeAC-Workshop, Grenoble, 24.-25. Januar 2002
  • S. Verdenhalven, H. Kühl: “Interfacing Concept for Different Levels of Abstraction in IP-based SoC Design”, Präsentation und Diskussion auf dem GI/ITG/GMM (VDE) Workshop ‘Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen’, Tübingen, 25.-27. Februar 2002
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  • Last modified: September 28, 2005 by Oliver Bringmann, FZI.